Tracker Acronyms
| Acronyms | Expansion |
Context |
|---|---|---|
| VIPRAM | Vertical Integrated Pattern Recognition Associative Memory | |
| 2S | Two Strip Sensor | |
| TMR | Triple Modular Redundancy | |
| TTA | Trigger Tower Architecture | |
| TDCS | Trigger Distribution and Control System | |
| Et | Transverse Energy | |
| TPG | Tracker Performance Group | |
| TOB | Tracker Outer Barrel | |
| TID | Tracker Inner Detector | |
| TEC | Tracker End Cap | |
| TK | Tracker | |
| TF | Track Fit | |
| TMT | Time-multiplexing Technique | |
| TTC | Time, Trigger and Control | |
| TH | Threashold | |
| THR | Threashold | |
| TDR | Technical Document Repository | |
| SSD | Solid State Drive | |
| SCT | Silicon Tracker | |
| SD | Silicon Detectors | |
| SPI | Serial Peripheral Interface | |
| FEB | same as DTC | |
| ROI | Region of Interest | |
| RTM | Rear Transition Module | |
| ROD | Read-out driver | |
| RO | Read-out | |
| RGH | Random Ghost Hits | |
| PPS | Precision Proton Spectrometer | |
| PX | Pixel | |
| PU | Pile-up | |
| POG | Physics Object Group | |
| PT | Pattern Track | |
| PRP | Pattern Recognition Platform | |
| PRM | Pattern Recognition Mezzanine | |
| PRE | Pattern Recognition Engine | |
| PRB | Pattern Recognition Board | |
| PMOS | P-type MOS | |
| CBC | ||
| CIC | ||
| DIB | ||
| FRN | ||
| HPK | ||
| MIC | ||
| MPA | ||
| NH | ||
| PV | ||
| TRG | ||
| TTS | ||
| MOS | Metal Oxide Semiconductor | |
| ML | Majority Logic | |
| lpGBT | low power GBT | |
| L1 | Level 1 | |
| I2C | Inter Integrated Circuit (bus) | |
| IPMI | Intelligent Platform Management Interface | |
| IPMC | Intelligent Platform Management Controller | |
| ID | Inner Detector | |
| HAPS | Hybrid Active Pixel Sensor | |
| HLT | High Level Trigger | |
| HCAL | Hadronic Calorimeter | |
| GPU | Graphics Processing Unit | |
| GT | Global Trigger | |
| GBT | Gigabit Transceiver | |
| GPGPU | General Purpose GPU | |
| FED | Front End Driver | |
| FE | Front End | |
| FMC | FPGA Mezzanine Card | |
| FTP | File Transfer Protocol | |
| FPGA | Field Programmable Gate Array | |
| FTK | Fast Tracker | |
| FR | Fake Rate | |
| EC | Endcap | |
| FPIX | End Cap of Pixel Detector | |
| ECAL | Electromagnetic Calorimeter | |
| Eff | Efficiency | |
| DT | Drift Tube | |
| DC | Don't Care (bits) | Associative Memory |
| DPG | Detector Performance Group | |
| DTC | Data Trigger and Control board | |
| DFS | Data Formatting System | |
| DF | Data Formatter | |
| DAQ | Data AcQuisition | |
| CAM | Content-Addressable-Memory | |
| CUDA | Compute Unified Device Architecture | |
| CMOS | Complementary MOS | |
| CPU | Central Processing Unit | |
| CSC | Cathode Strip Chambers | |
| BX | Bunch Cross | |
| BER | Bit Error Rate | |
| BPIX | Barrel of Pixel Detector | |
| BE | Back End | |
| AM | Associative Memory | |
| ASIC | Application-Spcific Integrated Circuit | |
| pt | angular momentum | |
| ATCA | Advanced Telecommunications Computing Architecture | |
| TIB | - Tracker Inner Barrel - Tracker Institution Board |
|
| TT | - Track Trigger - Trigger Tower |
|
| SS | - Silicon Strip - Super Strip |
|
| SCR | - Silicon Carrier Region - Silicon Controlled Rectifier |
|
| PR | - Pattern Recognition - Pattern Reconstruction |
|
| HPC | - High Performance Computing - High Pin Counting |
|
| PS | (Pixel + Strip) Sensor |
tecepe - 2014-07-29
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