Difference: SpracePublications (284 vs. 285)

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Summary of SPRACE Activities

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  • From September/2017 to September/2018 chaired the CMS HIN Publication Committee Board, together with Gunther Roland (MIT, Boston, EUA). In the period September/2018 to September/2019 chaired the same board together with Senta Victoria Greene (Vanderbilt University, Nashville, Tennessee). In September/2019 was invited by the Publication Committee Chair to continue in this position, together with Senta Victoria Greene (Vanderbilt University, Nashville, Tennessee).
  • Visited CERN to participate in the Heavy Ion run, from November 08 to December 03, 2018, a very active period for the heavy ion community, with at least two daily meetings attended daily in the group. Also present at CERN in this period were C\'esar A. Bernardes, FAPESP post-doctoral fellow, and Dener de Souza Lemos, PhD student with a FAPESP fellowship, both under my supervision. Their activities in this period will be described below.
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  • Actively contributed to the FSQ-14-002 analysis ("Study of Bose-Einstein correlations in pp, pPb, and PbPb collisions at the LHC "), which was published in December/2017 (Phys. Rev. C 97 (2018) 064912).
  • Actively contributed to the FSQ-15-009 analysis, approved in May, 2018. After that, the analysis completed the CWR and Final Reading procedures and sent for publication on October/20, 2019. During this period she supervised the FAPESP post-doctoral fellow, C\'esar A. Bernardes.
  • She is supervising contact person of the HIN-19-008 analysis ("Search for Electromagnetic Fields in PbPb Collisions at 5.02 TeV"), Dr. C\'esar A. Bernardes, which was recently approved and the preliminary results presented on Nov/05 at the Quark Matter 2019 conference.
  • She is supervising the Ph.D. student Dener de Souza Lemos, who is the contact person of the HIN-19-010 analysis ("K0sK0s femtoscopy in pPb collisions at 8.16 TeV").
  • Presented the plenary talk ``Femtoscopic BEC of charged hadrons in pp collisions at 13 TeV in CMS'' at the XIII Workshop on Particle Correlations and Femtoscopy (WPCF 2018), Krakow, Poland (2018).
  • Presented the plenary talk ``Results on Bose-Einstein correlations of charged hadrons in pp collisions at 13 TeV'' at the XIV Workshop on Particle Correlations and Femtoscopy (WPCF 2019), Dubna, Russia (2019).
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  • Actively contributed to the FSQ-14-002 analysis ("Study of Bose-Einstein correlations in pp, pPb, and PbPb collisions at the LHC "), which was published in December/2017 (Phys. Rev. C 97 (2018) 064912).
  • Actively contributed to the FSQ-15-009 analysis, approved in May, 2018. After that, the analysis completed the CWR and Final Reading procedures and sent for publication on October/20, 2019. During this period she supervised the FAPESP post-doctoral fellow, César A. Bernardes.
  • She is supervising contact person of the HIN-19-008 analysis ("Search for Electromagnetic Fields in PbPb Collisions at 5.02 TeV"), Dr. César A. Bernardes, which was recently approved and the preliminary results presented on Nov/05 at the Quark Matter 2019 conference.
  • She is supervising the Ph.D. student Dener de Souza Lemos, who is the contact person of the HIN-19-010 analysis ("K0sK0s femtoscopy in pPb collisions at 8.16 TeV").
  • Presented the plenary talk ``Femtoscopic BEC of charged hadrons in pp collisions at 13 TeV in CMS'' at the XIII Workshop on Particle Correlations and Femtoscopy (WPCF 2018), Krakow, Poland (2018).
  • Presented the plenary talk ``Results on Bose-Einstein correlations of charged hadrons in pp collisions at 13 TeV'' at the XIV Workshop on Particle Correlations and Femtoscopy (WPCF 2019), Dubna, Russia (2019).
 
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César Augusto Bernardes

  • During the PbPb data-taking in 2018, the Dr. C\'esar Augusto Bernardes was the outer tracker contact person of the CMS Heavy Ion. In this period, he was constantly in contact with the detector experts and the heavy-ions run coordinators. He presented daily reports about the issues and actions taken to solve the problems related to this sub-detector in the heavy-ion run meetings.
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  • Since September of 2019, C\'esar Augusto Bernardes has been nominated by the CMS Collaboration to coordinate the Flow and Correlation analysis group (Flow and Correlation PInG).
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  • Since September of 2019, C\'esar Augusto Bernardes has been nominated by the CMS Collaboration to coordinate the Flow and Correlation analysis group (Flow and Correlation PInG).
 
  • Analyses and service work (see details in the report by C\'esar A. Bernardes, attached at the end of the general report).

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Implementation of the GBT link in the uDTC firmware

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The GigaBit Transceiver x (GBTx) is a high-speed Application Specific Integrated Circuit (ASIC) designed for operation in high radiation environments, like those experienced in the center of LHC experiments. It provides a large number of electrical serial interfaces (ePorts) through which the other components of a detector front-end can communicate with the back-end electronics. These electrical signals, which can be monodirectional or bidirectional, are multiplexed by the GBTx into a high speed serial link, designed for operation with an optical transceiver, such as the radiation-resistant Versatile TRansceiver x (VTRx) used in our case. The optical connection runs through a pair of fibers and reaches the back-end board, where an optical transceiver is interfaced with a Field-Programmable Grid Array chip, hosting the read-out and control firmware. This firmware has to include a communication layer compatible with the one used by the GBT link protocol, such that data can be exchanged between the FPGA on the back-end board and the GBTx on the front-end module. This communication layer usually includes the GBT-FPGA firmware core developed by CERN. I worked on the integration of this core in the uDTC firmware, and established the correct configuration parameters to guarantee a reliable operation. uDTC is the official firmware used in CMS to develop the data acquisition framework for the tracker and to perform the testing and certification of the detector modules.
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The GigaBit Transceiver x (GBTx) is a high-speed Application Specific Integrated Circuit (ASIC) designed for operation in high radiation environments, like those experienced in the center of LHC experiments. It provides a large number of electrical serial interfaces (ePorts) through which the other components of a detector front-end can communicate with the back-end electronics. These electrical signals, which can be monodirectional or bidirectional, are multiplexed by the GBTx into a high speed serial link, designed for operation with an optical transceiver, such as the radiation-resistant Versatile TRansceiver x (VTRx) used in our case. The optical connection runs through a pair of fibers and reaches the back-end board, where an optical transceiver is interfaced with a Field-Programmable Grid Array chip, hosting the read-out and control firmware. This firmware has to include a communication layer compatible with the one used by the GBT link protocol, such that data can be exchanged between the FPGA on the back-end board and the GBTx on the front-end module. This communication layer usually includes the GBT-FPGA firmware core developed by CERN. I worked on the integration of this core in the uDTC firmware, and established the correct configuration parameters to guarantee a reliable operation. uDTC is the official firmware used in CMS to develop the data acquisition framework for the tracker and to perform the testing and certification of the detector modules.
 

Implementation of the SCA slow control protocol in the uDTC firmware

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Detector modules host a number of different configurable electronic components. For example, the outer tracker is composed of two types of modules, and each individual module hosts either 16 CBC and 2 CIC chips (2S modules) or 16 SSA, 16 MPA and 2 CIC chips (PS modules), each offering a rich set of configuration parameters, for a total size of many tens of kilobits. All these parameters are programmed using the Inter-Integrated chip Communication bus (I2C). This standard offers an advantage in terms of board resources, since it only requires two wires to be used for communicating with many chips, at the price of a higher complexity in the master circuit, which has to be implemented with special open-collector logic. The Slow Control Adapter (SCA) is a radiation-hard chip designed by CERN that responds to the various management needs of a detector module, like acting as an I2C, SPI or JTAG master, measuring voltages and temperatures, driving its pin in a configurable generic pattern, to name a few. The SCA is used on the current detector module prototypes. I worked on integrating into the uDTC firmware the GBT-SC core, which is used to control the SCA chip on the module, and to establish the configuration procedure to set it up for reliable operation. The setup used to integrate the GBTx control code into the uDTC firmware has also been used in the SCA code integration, as the VLDB card offers an SCA chip to be used for development. The implementation of optical read-out and control in uDTC via the GBTx and SCA chips in the first half of 2019 was a critical step in the commissioning of the module testing toolchain, such that it would be ready for the test beams planned in late 2019 and early 2020.
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Detector modules host a number of different configurable electronic components. For example, the outer tracker is composed of two types of modules, and each individual module hosts either 16 CBC and 2 CIC chips (2S modules) or 16 SSA, 16 MPA and 2 CIC chips (PS modules), each offering a rich set of configuration parameters, for a total size of many tens of kilobits. All these parameters are programmed using the Inter-Integrated chip Communication bus (I2C). This standard offers an advantage in terms of board resources, since it only requires two wires to be used for communicating with many chips, at the price of a higher complexity in the master circuit, which has to be implemented with special open-collector logic. The Slow Control Adapter (SCA) is a radiation-hard chip designed by CERN that responds to the various management needs of a detector module, like acting as an I2C, SPI or JTAG master, measuring voltages and temperatures, driving its pin in a configurable generic pattern, to name a few. The SCA is used on the current detector module prototypes. I worked on integrating into the uDTC firmware the GBT-SC core, which is used to control the SCA chip on the module, and to establish the configuration procedure to set it up for reliable operation. The setup used to integrate the GBTx control code into the uDTC firmware has also been used in the SCA code integration, as the VLDB card offers an SCA chip to be used for development. The implementation of optical read-out and control in uDTC via the GBTx and SCA chips in the first half of 2019 was a critical step in the commissioning of the module testing toolchain, such that it would be ready for the test beams planned in late 2019 and early 2020.
 

Full optical operation of the outer tracker modules in the uDTC firmware

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  The DTC board will need an IPMC, to manage its powering and to monitor its health while it is hosted inside the ATCA shelves in the CMS service cavern. Given the apparent absence of an open-source IPMC firmware solution compatible with the planned architecture for the DTC management chip (a Xilinx Zynq Ultrascale+ EG system on a chip), I organized the development at SPRACE of one such solution starting in late 2018 and currently in progress. The development program sees the participation of SPRACE Instrumentation Laboratory researchers, students from the department of electronic engineering at UNESP FEIS (Ilha Solteira, SP), students from Céntro Universitario FEI (São Bernardo do Campo, SP) and researchers from the Institute of Data Processing of the Karlsruhe Institute of Technology (KIT, Karlsruhe, Germany).
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The open source IPMC solution developed at SPRACE, which has been named OpenIPMC, has already been presented in meetings at CERN and got considerable attention from collaborators in the US and in Europe, as its open source nature eases debugging, customization and porting to other architectures. Currently the firmware is being developed on an Ultra96 development board by AVNET mated to a Pulsar-IIb ATCA board designed by Fermilab. An ATCA demonstrator board with more functions that will serve as an evolution to the current development board is being studied in collaboration with KIT researchers, and a first prototype is expected to be ready in January 2020.
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The open source IPMC solution developed at SPRACE, which has been named OpenIPMC, has already been presented in meetings at CERN and got considerable attention from collaborators in the US and in Europe, as its open source nature eases debugging, customization and porting to other architectures. Currently the firmware is being developed on an Ultra96 development board by AVNET mated to a Pulsar-IIb ATCA board designed by Fermilab. An ATCA demonstrator board with more functions that will serve as an evolution to the current development board is being studied in collaboration with KIT researchers, and a first prototype is expected to be ready in January 2020.
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  1. Apr/2018 : A pair of CERN FC7 boards is acquired by SPRACE to serve as development platforms for the development of the GBT link in the uDTC firmware.
  2. May/2018 : SPRACE becomes an official member of the Phase-2 Tracker Upgrade project.
  3. Sept/2018 : First successful board-to-board optical communication is established via the GBT link.
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  1. Oct/2018 : Beginning of the development of OpenIPMC, an open-source Intelligent Platform Media Controller (IPMC) firmware to be used in the future tracker back-end boards. LAR, AAS, AC and SFS from UNESP FEIS in Ilha Solteira join the effort bringing their experience from the Pulsar-2 IPMC.
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  1. Oct/2018 : Beginning of the development of OpenIPMC, an open-source Intelligent Platform Media Controller (IPMC) firmware to be used in the future tracker back-end boards. LAR, AAS, AC and SFS from UNESP FEIS in Ilha Solteira join the effort bringing their experience from the Pulsar-2 IPMC.
 
  1. Dec/2018 : A Versatile Link Demonstration Board, made available by the CERN CMS Detector Development Group, arrives in São Paulo.
  2. Jan/2019 : BC joins sprace on a Scientific Initiaion project, developing a firmware to measure the latency of the GBT optical link.
  3. Feb/2019 : Successful board-to-ASIC operation of the GBT link, between an FC7 and a VLDB board.
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  1. May/2019 : BC presents the results of the optical link latency measurement firmware in CMS Phase-2 tracker meetings.
  2. May-June/2019 : First tests of the optical firmware on a newly-arrived SErvice Hybrid (SEH), development of the control scripts for the SEH.
  3. June/2019 : Mating of the SEH to a 2S Front End Hybrid, development of the control scripts for the FEH. First optical readout of data from the module by the EP-CMX-DA group at CERN using our firmware.
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  1. Sept/2019 : The first version of OpenIPMC is presented in CMS Phase-2 tracker meetings.
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  1. Sept/2019 : The first version of OpenIPMC is presented in CMS Phase-2 tracker meetings.
 
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Personnel

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The Associative Memory Alternative for the CMS Phase-2 Track Finder

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--+++ Timeline of SPRACE Involvement
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Timeline of SPRACE Involvement

 
  1. Jun/2014 : SPRACE-Fermilab collaboration kick-off with the visit of AAS, EMG, MVSF and SFN to Ted Liu’s AM+FPGA group.
  2. Oct/2014-Apr/2015 : LAR and TCP worked at Fermilab on the Pulsar II ATCA hardware that was develop at Fermilab. They implemented a control system known as Intelligent Platform Management Interface (IPMI), required by the ATCA Standard. They also implemented the required network and protocols necessary to remotely program the Pulsar 2b FPGA. Both functions were implemented in a micro-controller of the board. Although the team has good experience in the ATCA environment, if necessary, they may be involved in the development of micro-TCA systems. Several Internal Notes were published by them: XVC Service a New IPMC Functionality ( SIN-R 01/2014), Multiple ATCA Shelves Control Topology ( SIN-R 01/2015), and ATCA/IPMI Service A New Pulsar 2b IPMC Functionality ( SIN-R 02/2015).
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  The CMS Trigger and Data Acquisition (DAQ) System (TriDAS) was designed to inspect the detector information at the full LHC crossing frequency of 40 MHz and to select events at a maximum rate of O(10^2) Hz for archiving and later offline analysis. The required rejection power of O(10^5) is too large to be achieved in a single processing step, if a high efficiency is to be maintained for the physics phenomena CMS studies. For this reason, the full selection task is split into 2 steps. The first step is the Level-1 Trigger (L1T), a synchronous FPGA-based system designed to reduce the rate of events accepted for further processing to less than 100 kHz. The second step is the High-Level Trigger (HLT), an asynchronous software-based suite of algorithms designed to reduce this maximum Level-1 Accept (L1A) rate of 100 kHz to a final output rate of approximately 1 kHz; the algorithms are implemented in the offline CMS software framework (CMSSW) running in commodity CPUs.
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The High-Luminosity LHC (HL-LHC) is a proposed upgrade of the accelerator, bringing the instantaneous luminosity delivered to experiments to 75 Hz/nb and its centre-of-mass energy to the design value of 14 TeV. Over the proposed operation period of the HL-LHC, from 2026 to 2035, this will entail a twenty-fold increase of the produced data. The total pp collision dataset delivered by the LHC to the general-purpose experiments, including the upgrade era, amounts to 3000 fb-1 (3 ab-1) of integrated luminosity. All aspects of the experiments will have to undergo essential improvements, in what is known as the Phase-II upgrade, to maintain good physics performance during the high-luminosity operation. These include both engineering upgrades to the detectors to withstand the increased radiation levels and operational upgrades to address the extraordinary amounts of data produced.
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The High-Luminosity LHC (HL-LHC) is a proposed upgrade of the accelerator, bringing the instantaneous luminosity delivered to experiments to 75 Hz/nb and its centre-of-mass energy to the design value of 14 TeV. Over the proposed operation period of the HL-LHC, from 2026 to 2035, this will entail a twenty-fold increase of the produced data. The total pp collision dataset delivered by the LHC to the general-purpose experiments, including the upgrade era, amounts to 3000 fb^-1 (3 ab^-1) of integrated luminosity. All aspects of the experiments will have to undergo essential improvements, in what is known as the Phase-II upgrade, to maintain good physics performance during the high-luminosity operation. These include both engineering upgrades to the detectors to withstand the increased radiation levels and operational upgrades to address the extraordinary amounts of data produced.
 
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The L1T Technical Design Report is nearing its completion and will be released in the first quarter of 2020. It will be focused on the development of a new L1T that leverages the whole suite of CMS detector upgrades: extended tracker coverage, L1 Track Trigger capabilities, new electronics for the calorimeters, new muon stations. The HLT upgrade will be a part of DAQ Technical Design report and will be focused on demonstrating a path to a Phase-II High Level Trigger Menu that supports the CMS physics program. It will include efficiency, rate and timing considerations and extrapolations to the real Run 4 system; the usage of new technologies, like general-purpose GPUs and machine learning techniques, will play an integral part on the development.
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The L1T Technical Design Report is nearing its completion and will be released in the first quarter of 2020. It will be focused on the development of a new L1T that leverages the whole suite of CMS detector upgrades: extended tracker coverage, L1 Track Trigger capabilities, new electronics for the calorimeters, new muon stations. The HLT upgrade will be a part of DAQ Technical Design report and will be focused on demonstrating a path to a Phase-II High Level Trigger Menu that supports the CMS physics program. It will include efficiency, rate and timing considerations and extrapolations to the real Run 4 system; the usage of new technologies, like general-purpose GPUs and machine learning techniques, will play an integral part on the development.
 
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R&D Associated Projects

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R&D Associate Projects

 
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Presentations

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Experimental Physics Responsibility (EPR)

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Computing: Processing and Storage

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Detailed Monitoring of BR-SP-SPRACE WLCG Tier 2 via Grafana
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Detailed Monitoring of BR-SP-SPRACE WLCG Tier 2 via Grafana
 
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SPRACE in the Press

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